A novel dynamic reconfigurable VLSI architecture for H.264 transforms

The 4times4 integer transforms are adopted in the MPEG-4 AVC /H.264 standard. In this paper, two novel signal flow graphs of the 4times4 forward and inverse transforms for H.264 are proposed. A new dynamic reconfigurable architecture without using transpose memory for the multiple transforms is proposed on the basis of the new SFGs. Our design is implemented with 0.18 mum CMOS technology. Under a clock frequency of 200 Mhz, the architecture allows the real-time processing of 4096times2048 at 30 fps with the area cost of 5140 gates and the power dissipation of 15.64 mW.