VHDL modeling and simulation of a VLSI architecture for 2-D signal processing

The authors describe a processor architecture for 2-D signal processing that uses the VHSOC hardware description language (VHDL). A behavioral-level model and functional-level model are developed and simulated. These models are useful in assessing the system performance before building. In the behavioral level we describe the logic and timing of the architecture, while on the functional level we describe the hardware components of the processor. A VHDL simulator is used to verify the behavior and functioning of the processor