An inverter output filter to mitigate dV/dt effects in PWM drive system

High switching frequencies and small rise times are common with modern switching devices. These parameters, especially the rise time, are known to have undesired side effects such as excessive voltage stress on windings, motor leakage currents, bearing currents, conducted EMI, etc. Furthermore, if long cables are used to connect the inverter and the motor, the rapid rise times cause the transmission line effect, which can double the voltage applied to the motor terminals. In this paper a new inverter output filter to mitigate these problems is presented. The filter topology has the advantage of being easy to implement on existing ASDs as an add-on option and it reduces both common and differential mode dV/dt simultaneously. Its effectiveness is shown analytically via simulations and by experimental results on a 20 kW ASD