Low-overhead design technique for calibration of maximum frequency at multiple operating points

Determination of maximum operating frequencies (F_max) during manufacturing test at different operating voltages is required to: (a) to ensure that, for a dynamic voltage and frequency scaling (DVFS) system, the adaptation hardware actually applies the correct operating frequency corresponding to a scaled supply and (b) to sort chips in different voltage-frequency (V-F_max)bins, so that chips at different bins can be used for different applications. Existing speed binning approach requires extensive delay testing at all operating points with all possible frequencies, which increases test cost and test time significantly. In this paper, we propose a low-overhead solution for characterising F_max of a circuit at Afferent operating voltages that can eliminate the complex and expensive F_max calibration at multiple voltage points. The basic idea is to choose a small set of representative paths in a circuit based on their voltage sensitivity and dynamically configuring them into ring oscillator to compute the F_max. The proposed calibration mechanism is all-digital, robust to process variations, reasonably accurate (average 2.8% error) and incorporates minimal hardware overhead (average 1.7% delay. 3.5% area and 0.28%power overhead).