Title :
Efficient path delay test generation based on stuck-at test generation using checker circuitry
Author :
Iwagaki, Tsuyoshi ; Ohtake, Satoshi ; Kaneko, Mineo ; Fujiwara, Hideo
Author_Institution :
Japan Adv. Inst. of Sci. & Technol. (JAIST), Ishikawa
Abstract :
This paper proposes an approach to non-robust and functionally sensitizable path delay test generation through stuck-at test generation. In this approach, to generate two-pattern tests for path delay faults in a combinational circuit, checker circuitry is constructed which is composed of logic gates corresponding to the mandatory assignments for detecting the faults. This checker circuitry allows us to use any existing combinational stuck-at test generation tool. Since today´s stuck-at test generation tools reach a mature level, the proposed approach can efficiently solve the path delay test generation problem for combinational circuits. Experimental results show that the approach can speed up path delay test generation and can improve fault efficiency. This paper also discusses how a scan circuit and the issues of over-testing and test power are handled in the proposed test generation framework.
Keywords :
automatic test pattern generation; combinational circuits; fault diagnosis; logic gates; logic testing; checker circuitry; combinational circuits; combinational stuck-at test generation tool; fault detection; logic gates; path delay test generation problem; two-pattern test generation; Automatic test pattern generation; Circuit faults; Circuit testing; Combinational circuits; Delay; Electronic mail; Information science; Inverters; Logic testing; Multivalued logic;
Conference_Titel :
Computer-Aided Design, 2007. ICCAD 2007. IEEE/ACM International Conference on
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-1381-2
Electronic_ISBN :
1092-3152
DOI :
10.1109/ICCAD.2007.4397301