DocumentCode :
2330993
Title :
Timing variation-aware high-level synthesis
Author :
Jung, Jongyoon ; Kim, Taewhan
Author_Institution :
Seoul Nat. Univ., Seoul
fYear :
2007
fDate :
4-8 Nov. 2007
Firstpage :
424
Lastpage :
428
Abstract :
The timing closure problem is one of the most important problems in the design automation. However, the rapid increase of the impact of the process variation on circuit timing makes the problem much more complicated and unpredictable to tackle in synthesis. This work addresses a new problem of high-level synthesis (HLS) that effectively takes into account the timing variation. Specifically, the work addresses the following four problems: (1) how can the statistical static timing analysis (SSTA) used in logic synthesis be modified and applied to the delay and yield computation in HLS? (2) how does the resource binding affect yield? (3) how does the scheduling affect yield? (4) how can scheduling and resource binding tasks be combined together to efficiently solve the problem with the objective of minimizing latency under yield constraint?
Keywords :
electronic design automation; high level synthesis; statistical analysis; circuit timing; high-level synthesis; logic synthesis; statistical static timing analysis; timing closure problem; Clocks; Computer science; Delay effects; Design automation; High level synthesis; Job shop scheduling; Logic; Processor scheduling; Timing; Yield estimation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer-Aided Design, 2007. ICCAD 2007. IEEE/ACM International Conference on
Conference_Location :
San Jose, CA
ISSN :
1092-3152
Print_ISBN :
978-1-4244-1381-2
Electronic_ISBN :
1092-3152
Type :
conf
DOI :
10.1109/ICCAD.2007.4397302
Filename :
4397302
Link To Document :
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