Adaptive post-silicon tuning for analog circuits: concept, analysis and optimization

The well-known Pelgrom model (S. Ray and B. Song, 2006) has demonstrated that the variation between two devices on the same die due to random mismatch is inversely proportional to the square root of the device area: sigma ~ 1/sqrt(Area). Based on the Pelgrom model, analog devices are sized to be large enough to werage out random variations. Importantly, with CMOS scaling, variations due to random doping fluctuations are making it exceedingly difficult to control device mismatches by sizing alone; namely, the devices have to be made so large that the benefits of CMOS scaling are not realized for analog and RF circuits. In this paper we propose a novel post-silicon timing methodology to reduce random mismatches for analog circuits in sub-90 nm CMOS. A novel dynamic programming algorithm is incorporated into a fast Monte Carlo simulation flow for statistical analysis and optimization of the proposed tunable analog circuits. We apply the proposed post-silicon tuning methodology to several commonly-used analog circuit blocks. We demonstrate that with the post-silicon tuning, device mismatch exponentially decreases as area increases: sigma-exp(-alpha-Area).