Toward full fluctuation analysis of small FETs

We, for the first time, estimate total fluctuation resulting from random dopants, interface traps and work functions using experimentally calibrated 3D statistical device simulation on 16-nm-gate high-κ/metal gate planar and bulk FinFET devices. The total full 3D simulated threshold voltage fluctuation (σV_th), induced by the aforementioned random sources simultaneously, is different from their statistical total sum because the assumption of independently and identically distributed random variables is invalid owing to strong surface potential´s interactions among them. Structural innovation using bulk FinFET implies significant fluctuation suppression, which is about 45.6% reduction on σV_th. 3D vertical channel-based device provides good capability in fluctuation reduction, compared with process efforts on low interface trap density (e.g., D_it is below 10¹¹ eV^-1 cm^-2) and small grain size (e.g., 1×1 nm²) of metal gate on planar one.