DocumentCode :
2331593
Title :
The "(4,2)-concept" fault tolerant computer
Author :
Krol, Th.
fYear :
1995
fDate :
27-30 June 1995
Firstpage :
32
Abstract :
This paper describes a new fault-tolerant computer architecture based on a "distributed implementation" of a symbol-error correcting code. In this so-called (4,2)-concept the faults are masked by means of this code. The memory hardware has been doubled because each data word is stored after encoding into four symbols, two of which being redundant. All the processing functions have been quadrupled, which requires the use of four microprocessors. The hardware is partitioned into four slices. Any slice failure is masked by the code. By application of a newly designed error correcting code, the basic (4,2)-concept has been extended with a special mode in which single-bit faults are masked even in the presence of a completely failing slice. The (4,2)-concept will be applied in the Philips PRX-D digital telephone exchange.
Keywords :
Circuit faults; Computer architecture; Error correction codes; Fault detection; Fault tolerance; Hardware; Laboratories; Microprocessors; Redundancy; Telephony;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Fault-Tolerant Computing, 1995, Highlights from Twenty-Five Years., Twenty-Fifth International Symposium on
Conference_Location :
Pasadena, CA
Print_ISBN :
0-8186-7150-5
Type :
conf
DOI :
10.1109/FTCSH.1995.532608
Filename :
532608
Link To Document :
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