Co-evaluation of power supply noise of CMOS microprocessor using on-board magnetic probing and on-chip waveform capturing techniques

Author

Sasaki, Yuta ; Yoshikawa, Kumpei ; Nagata, Makoto ; Ichikawa, Kouji

Author_Institution

Grad. Sch. of Syst. Inf., Kobe Univ., Kobe, Japan

fYear

2012

fDate

9-11 May 2012

Firstpage

1

Lastpage

2

Abstract

On-chip and on-board power noise measurements were performed on a 32-bit microprocessor core in a 90-nm CMOS technology. The on-chip voltage noise and on-board near-field magnetic field measurements are related to each other with a unified power delivery network that is formed by on-chip and on-board parasitic components. The significant importance of LSI chip-package-board co-simulation is also discussed from the measurement results.

Keywords

CMOS integrated circuits; integrated circuit measurement; integrated circuit noise; integrated circuit packaging; large scale integration; microprocessor chips; power supply circuits; CMOS microprocessor; CMOS technology; LSI chip-package-board cosimulation; on-board magnetic probing; on-board near-field magnetic field measurements; on-board parasitic components; on-board power noise measurements; on-chip voltage noise; on-chip waveform capturing techniques; power supply noise coevaluation; size 90 nm; word length 32 bit; Current measurement; Magnetic field measurement; Noise; Noise measurement; Power supplies; Semiconductor device measurement; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

Future of Electron Devices, Kansai (IMFEDK), 2012 IEEE International Meeting for

Conference_Location

Osaka

Print_ISBN

978-1-4673-0837-3

Type

conf

DOI

10.1109/IMFEDK.2012.6218586

Filename

6218586