An efficient wake-up schedule during power mode transition considering spurious glitches phenomenon

During the power mode transition, a large surge current may lead to the malfunctions in a power-gating design. In this paper, we introduce several important properties of the surge current during the power mode transition for the distributed sleep transistor network (DSTN) designs. Based on these properties, we propose an accurate estimation of surge current and provide an efficient schedule on the DSTN structure. Our experiment achieved significantly better results than previous works - on average, 332 times wake-up time reduction and 35.48% less energy loss during the power mode transition.