A new single electron tunneling cell based on linear threshold gate

The continuing scaling down and miniaturization of CMOS devices has led researchers now to build new devices with very small dimensions (nanotechnology), whose behavior will be interpreted based on quantum mechanics. Single electron devices (SEDs) promise excellent potential for future ultra large scale integrated (ULSI) circuits due to their potential for low power consumption and their small size. Considerable effort has been expended over the past decade, or so, in the understanding of the physical principles of SED operation and then different structures and topologies are proposed for implementing logic gates as applications of them. One of these structures is the linear threshold gate (LTG). The presented threshold gate, however, does not operate correctly in a complex network due to the passive nature of the circuit. For solving this problem the output of the threshold gate should be augmented with a SET buffer/inverter. The purpose of this paper is to introduce a single electron tunneling (SET) cell based on LTG for applications in complex circuit designs. The proposed cell accepts three signals as its inputs and produces three-input NAND, NOR, XOR and Majority function as its output. In this paper also a new method for implementing a three-input XOR function is introduced.