Title :
Design methodology for fault tolerant ASICs
Author :
Petrovic, Vladimir ; Ilic, Marko ; Schoof, Gunter ; Stamenkovic, Zoran
Author_Institution :
IHP, Frankfurt Oder, Germany
Abstract :
The sensitivity of application specific integrated circuits (ASICs) to the single event effects (SEE) can induce failures of the systems which are exposed to increased radiation levels in the space and on the ground. This paper presents a design methodology for a full fault tolerant ASIC that is immune to the single event upsets (SEU) in sequential logic, the single event transients (SET) in combinational logic and the single event latchup (SEL). The dual modular redundancy (DMR) and a SEL power-switch (SPS) are the basis for a modified ASIC design flow. Measurement results have proven the correct functionality of DMR and SPS circuits, as well as a high fault tolerance of implemented ASICs along with moderate overhead in respect of power consumption and occupied silicon area.
Keywords :
application specific integrated circuits; combinational circuits; fault tolerance; integrated circuit design; integrated circuit reliability; redundancy; sequential circuits; DMR; SEE; SEL power-switch; SET; SEU; SPS circuit; application specific integrated circuit sensitivity; combinational logic; dual modular redundancy; fault tolerant ASIC; modified ASIC design flow; power consumption; radiation levels; sequential logic; single event effects; single event latchup; single event transients; single event upsets; Application specific integrated circuits; Circuit faults; Fault tolerance; Fault tolerant systems; Libraries; Single event upset; Standards; ASIC design methodology; Single event effect; dual modular redundancy; fault tolerance; power switch;
Conference_Titel :
Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2012 IEEE 15th International Symposium on
Conference_Location :
Tallinn
Print_ISBN :
978-1-4673-1187-8
Electronic_ISBN :
978-1-4673-1186-1
DOI :
10.1109/DDECS.2012.6219014
