Title :
Self-aligned nanostructures by CMOS technology
Author :
Bien, Daniel C S ; Lee, Hing Wah ; Saman, Rahimah Mohd ; Badaruddin, Siti Aishah Mohamad ; Zain, Azlina Mohd ; Teh, Aun Shih
Author_Institution :
MEMS/NEMS Cluster, MIMOS BERHAD, Kuala Lumpur, Malaysia
Abstract :
In this paper, the authors demonstrate a method to produce nanostructures and nanowires with dimensions down to 10nm by a self-alignment process using the standard CMOS spacer technology. In this process, very accurate alignment is achieved because the alignment is not determined by the lithographic tool but by the structures and materials themselves. The spacer technique is commonly used in the fabrication of nanometer transistor and does not require the use of submicron lithographic tools. As illustrated in Figure 1, arrays of polysilicon nanostructures have been fabricated on 8" silicon wafers. These include ultra fine structures down to 20nm with an aspect ratio of 10:1, and 10nm structures with an aspect ratio of 20:1. In this process, very accurate alignment is achieved. The formed polysilicon nanostructures can be used as an etch mask to transfer fine patterns to insulating materials such as silicon nitride (Si3N4) which in turns is used as a mask for bulk machining of deep silicon structures as shown in Figure 2. The fabricated polysilicon nanowires were phosphorous doped to characterize the effect of length and diameter on the wire resistance. The resistance of the nanowires was found to increase linearly when varying the wire length from 20 to 500nm where the diameter of the nanowires has a significant impact to the wire resistance when its diameter is less than 50nm.
Keywords :
CMOS integrated circuits; electrical resistivity; elemental semiconductors; machining; masks; nanofabrication; nanowires; phosphorus; semiconductor doping; semiconductor growth; silicon; Si; Si:P; aspect ratio; bulk machining; deep silicon structures; etch mask; fine pattern transfer; insulating materials; nanowires; phosphorous doping; polysilicon nanostructured arrays; self-aligned nanostructures; silicon nitride; silicon wafers; size 20 nm; size 8 inch; standard CMOS spacer technology; ultrafine structures; wire length; wire resistance;
Conference_Titel :
Enabling Science and Nanotechnology (ESciNano), 2010 International Conference on
Conference_Location :
Kuala Lumpur
Print_ISBN :
978-1-4244-8853-7
DOI :
10.1109/ESCINANO.2010.5701055