SPC04-1: Quality-Energy Scalable Chip Level Equalization for HSDPA

Quality-Energy scalability has been proved to be an effective technique toward the cost reduction for signal processing. However, although it has large potentials for reducing signal processing energy in wireless transceivers, it has not yet been applied to them. In this paper, we elaborate an example and present a feedback control scheme to achieve Quality-Energy scalability for the chip level equalization in High Speed Downlink Packet Access (HSDPA) receivers. In conventional equalizers, the coefficients are updated according to the worst-case assumption that the channel is very dynamic. In our proposed approach, we take into account the speed of the channel variation to adapt the updating frequency. Specifically, a low-complexity closed-loop controller is designed to vary the update-interval while limiting the maximum equalization error. The proposed control scheme takes high order channel statistics implicitly into account without the need for an explicit estimator. Simulation results show that the Quality-Energy scalability for the equalizer results in significant energy reduction with minor quality degradation for channels with large coherence times. Specifically, for a pedestrian channel, 60% of the signal processing operations, and hence energy, can be saved with only 0.25 dBBERloss.