A three-dimensional DRAM using floating body cell in FDSOI devices

Author

Liu, Xuelian ; Zia, Aamir ; LeRoy, Mitchell R. ; Raman, Srikumar ; Clark, Ryan ; Kraft, Russell ; McDonald, John F.

Author_Institution

Center for Integrated Electron., Rensselaer Polytech. Inst., Troy, NY, USA

fYear

2012

fDate

18-20 April 2012

Firstpage

159

Lastpage

162

Abstract

This paper describes the capacitorless 1-transistor (1T) DRAMs exploits the floating body (FB) effect of Fully depleted (FD) SOI devices, where the transistor body is used as a charge storage node. A novel three-tier, 3D, 1T embedded DRAM is presented that can be vertically integrated with the microprocessor achieving low cost, high density on-chip main memory. A 394Kbits test chip is designed and fabricated in a 0.15um fully depleted SOI CMOS process. The measured retention time under holding conditions is higher than 10ms. In the continuous read mode, every read should be followed by a refresh. The test chip is designed to work with an access time of 50ns and operates at 10MHz.

Keywords

CMOS memory circuits; DRAM chips; silicon-on-insulator; transistors; FDSOI device; SOI CMOS process; capacitorless 1-transistor; charge storage node; floating body cell; frequency 10 MHz; fully depleted SOI device; microprocessor; size 0.15 micron; three-dimensional DRAM; time 50 ns; Arrays; Logic gates; Microprocessors; Random access memory; Three dimensional displays; Transistors; 3D integration; FD-SOI; capacitorless 1T DRAM; floating body cell; memory stack;

fLanguage

English

Publisher

ieee

Conference_Titel

Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2012 IEEE 15th International Symposium on

Conference_Location

Tallinn

Print_ISBN

978-1-4673-1187-8

Electronic_ISBN

978-1-4673-1186-1

Type

conf

DOI

10.1109/DDECS.2012.6219044

Filename

6219044