Design of 18-bit decimator for sigma-delta analog to digital converter with variable oversampling rate for audio application

Author

Gerasta, Olga Joy L. ; Villaruz, Harrez ; Cagadas, Dominic O.

Author_Institution

Coll. of Eng., MSU-Iligan Inst. of Technol., Iligan, Philippines

fYear

2014

fDate

12-16 Nov. 2014

Firstpage

1

Lastpage

6

Abstract

An 18-bit decimator design for sigma-delta analog to digital converter with variable oversampling rate for audio application was successfully implemented in TSMC 0.13 um Logic CMOS Technology. Behavioral model of this project is implemented using MATLAB and actual implementation using RTL Code with the aid of Verilog Compiler Simulator. The oversampling rates used in this decimator design are 32, 64, 128 and 256. Also, this decimator uses 1 sinc filter and 2 halfband filters as the main blocks for the whole system. The result of the design actually minimized the delay of the signal as compared to the behavioral simulation obtained. The total cell area is reduced reaching the desirable signal-to-noise ratio.

Keywords

CMOS logic circuits; analogue-digital conversion; audio signal processing; filters; integrated circuit design; MATLAB; RTL code; TSMC logic CMOS technology; audio application; decimator design; halfband filters; sigma-delta analog to digital converter; signal-to-noise ratio; sinc filter; size 0.13 mum; variable oversampling rate; verilog compiler simulator; Band-pass filters; Clocks; Finite impulse response filters; MATLAB; Read only memory; Timing; Decimator; delta-sigma modulator; halfband filter; oversampling rate; sinc filter;

fLanguage

English

Publisher

ieee

Conference_Titel

Humanoid, Nanotechnology, Information Technology, Communication and Control, Environment and Management (HNICEM), 2014 International Conference on

Conference_Location

Palawan

Print_ISBN

978-1-4799-4021-9

Type

conf

DOI

10.1109/HNICEM.2014.7016227

Filename

7016227