DocumentCode
2334609
Title
On the impact of dishing in metal CMP processes on circuit performance
Author
Stine, Brian E. ; Vallishayee, Rakesh
Author_Institution
PDF Solutions Inc., San Jose, CA, USA
fYear
1998
fDate
35953
Firstpage
64
Lastpage
67
Abstract
In this paper, we explore the impact of dishing in metal CMP processes on circuit performance. The impact on power distribution networks and clock distribution networks, critical components in modern VLSI designs, is of specific interest. For the two examples given in this paper, we find the impact to be very small
Keywords
VLSI; chemical mechanical polishing; clocks; integrated circuit interconnections; integrated circuit metallisation; integrated circuit reliability; integrated circuit yield; semiconductor process modelling; surface topography; VLSI design; circuit performance; clock distribution networks; dishing; metal CMP processes; power distribution networks; Capacitance; Circuit optimization; Clocks; Contact resistance; Delay; Intelligent networks; Power supplies; SPICE; Voltage; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
Statistical Metrology, 1998. 3rd International Workshop on
Conference_Location
Honolulu, HI
Print_ISBN
0-7803-4338-7
Type
conf
DOI
10.1109/IWSTM.1998.729772
Filename
729772
Link To Document