Digital-driven formal analog verification for asynchronously feed-backed circuitries

In this paper we show a road map for successively dividing an asynchronously feed-backed circuitry into its substructures, and provide several intuitive and formal approaches to recompose structural behavior from its substructures. Each dividing granularity and composition provides specific information about safety, stability, reliability and reproducibility. We further classify and discuss behavioral model and stability criteria on bases of the given structural properties and present a use-case. Implementation results are given and discussed formally with respect to extracted structure-weaknesses and safety aspects. The method exhibits analog properties of the structure like multivalued information flow, propagation time and superpositions that can lead to information corruptness.