Title :
Low power scan by partitioning and scan hold
Author :
Arvaniti, Efi ; Tsiatouhas, Yiorgos
Author_Institution :
Dept. of Comput. Sci., Univ. of Ioannina, Ioannina, Greece
Abstract :
Scan testing dynamic power consumption can induce reliability problems in the circuit under test (CUT) during manufacturing testing. In this paper, we propose a scan chain partitioning technique, supported by a scan hold mechanism, for low power dissipation during the shift phase of the scan testing procedures. Substantial power reductions can be achieved either in built-in self test (BIST) or non-BIST scan-based testing environments, without test application time increase, fault coverage decrease, scan cell reordering and clock gating.
Keywords :
built-in self test; design for testability; integrated circuit testing; power consumption; CUT; built-in self test; circuit under test; clock gating; fault coverage; low power dissipation; low power scan; manufacturing testing; nonGIST scan-based testing; reliability problems; scan cell reordering; scan chain partitioning technique; scan hold mechanism; scan testing dynamic power consumption; scan testing procedures; substantial power reductions; Built-in self-test; Clocks; Computer architecture; Microprocessors; Power demand; Vectors; design for test (DfT); low power DfT; scan-based test;
Conference_Titel :
Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2012 IEEE 15th International Symposium on
Conference_Location :
Tallinn
Print_ISBN :
978-1-4673-1187-8
Electronic_ISBN :
978-1-4673-1186-1
DOI :
10.1109/DDECS.2012.6219070
