DocumentCode :
2335056
Title :
BTI impact on logical gates in nano-scale CMOS technology
Author :
Khan, Seyab ; Hamdioui, Said ; Kukner, Halil ; Raghavan, Praveen ; Catthoor, Francky
Author_Institution :
Comput. Eng. Lab., Delft Univ. of Technol., Delf, Netherlands
fYear :
2012
fDate :
18-20 April 2012
Firstpage :
348
Lastpage :
353
Abstract :
As semiconductor manufacturing has entered into the nanoscale era, Bias Temperature Instability (BTI) -Negative BTI (NBTI) in PMOS transistors and Positive BTI (PBTI) in NMOS transistors- has become one of the most serious aging mechanisms that reduces reliability of logic gates. This paper presents a simulation-based BTI analysis in both basic (such as NAND and NOR) and complex gates while considering the impact of input´s duty cycle, the frequency at which they change, as well as the impact of the stressed transistor location. The simulation results show that the impact of BTI is strongly gate dependent and that in general the impact in complex gates is larger. When considering both NBTI and PBTI for basic gates, the results reveal that for a NOR gate the impact of NBTI is 2.19× higher than that of PBTI; while for a NAND gate, PBTI impact is 1.27× higher than that of NBTI. When considering different input duty cycles and their frequencies, the results show that the higher the duty cycle, the lower NBTI impact and the higher the PBTI impact regardless of the gate types and the frequency; a variation of ±30% duty cycle causes a variation of up to 49% variation in the impact of NBTI and a variation of 16% in the impact of PBTI. For complex gates, the results show similar trends, but with higher impact.
Keywords :
CMOS integrated circuits; integrated circuit modelling; logic gates; nanoelectronics; NMOS transistors; NOR gate; PMOS transistors; bias temperature instability; logical gates; nanoscale CMOS technology; negative BTI; positive BTI; Degradation; Delay; Logic gates; MOSFETs; Organizations; Stress; Complex gates; NBTI; PBTI; duty cycle; frequency; stress location;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2012 IEEE 15th International Symposium on
Conference_Location :
Tallinn
Print_ISBN :
978-1-4673-1187-8
Electronic_ISBN :
978-1-4673-1186-1
Type :
conf
DOI :
10.1109/DDECS.2012.6219086
Filename :
6219086
Link To Document :
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