Reduction of timed marked graphs and its applications to manufacturing systems

Marked graphs are an important class of Petri nets for modeling asynchronous concurrent systems. Their reduction theory has been well established. To evaluate the cycle time and other performance measures, their places and/or transitions can be associated with deterministic timing information. Analytical formulas are well known based on all loops in the graph. They have been used to derive the cycle time of a shop-floor production system, a robotic assembly system, and a flexible manufacturing system cell. It is observed that a marked graph model grows with the system size and results in a complexity problem to find all the loops inside the model. To challenge this problem, the paper proposes a reduction theory and algorithm for timed marked graphs. Thus the stepwise reduction of timed marked graphs can be performed efficiently. This method has been used to evaluate a flexible manufacturing system (FMS) cell