A VLSI systolic filter with ternary coefficients for delta-modulated signals

Author

Terreni, P. ; Roncella, R. ; Picchi, G. ; Saletti, R.

Author_Institution

Istituto di Elettronica e Telecomunicazioni, Pisa Univ., Italy

fYear

1988

fDate

7-9 June 1988

Firstpage

1767

Abstract

The realization of a digital FIR (finite impulse response) filter for both input data and coefficients encoded with ternary levels by delta-sigma modulation (DSM) is described. Due to the ternary values, multibit calculations are not needed. The filter architecture is very regular, highly parallel, and pipelines. The filter is easily made adaptive, as coefficients can be changed during normal operation. It is composed of bit-level systolic arrays whose cells are designed to allow a working frequency and consequently a throughput rate close to the limit of the technology used. A filter with 160 taps was realized in a 3- mu m H-CMOS technology.<>

Keywords

CMOS integrated circuits; VLSI; adaptive filters; delta modulation; digital filters; digital signal processing chips; parallel processing; pipeline processing; 160 tap configuration; 3 micron; DSM; H-CMOS technology; VLSI systolic filter; adaptive filter; bit-level systolic arrays; delta-modulated signals; delta-sigma modulation; digital FIR filter; finite impulse response; parallel pipelined architecture; ternary coefficients; Adaptive filters; Clocks; Computer architecture; Concurrent computing; Delta modulation; Finite impulse response filter; Frequency; Systolic arrays; Throughput; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1988., IEEE International Symposium on

Conference_Location

Espoo, Finland

Type

conf

DOI

10.1109/ISCAS.1988.15277

Filename

15277