Title :
Design of analog and digital error detector systems
Author_Institution :
Faculty of Eng., Menouf
Abstract :
In this paper, a theoretical design of an error detecting system which can be used to measure the bit error rate in the repeaters of digital transmission systems with binary block codes of bounded digital sum is described. Any crossing to such bounds due to an error leads to violations after a certain time. Moments of detecting these violations as well as the interval time between them are computed. The detecting system is designed in both analog and digital circuits with acceptable circuit complexity and low power consumptions
Keywords :
data communication equipment; digital communication; error detection codes; fault diagnosis; repeaters; analog error detector; binary block codes; bit error rate; bounded digital sum; circuit complexity; digital error detector; digital transmission systems; interval time; low power consumptions; repeaters; theoretical design; Bandwidth; Bit error rate; Block codes; Complexity theory; Costs; Detectors; Digital circuits; Energy consumption; Monitoring; Repeaters;
Conference_Titel :
Instrumentation and Measurement Technology Conference, 1994. IMTC/94. Conference Proceedings. 10th Anniversary. Advanced Technologies in I & M., 1994 IEEE
Conference_Location :
Hamamatsu
Print_ISBN :
0-7803-1880-3
DOI :
10.1109/IMTC.1994.351843
