DocumentCode :
2337063
Title :
Design of portable hearing aid based on FPGA
Author :
Min, Yang
Author_Institution :
Electron. Eng. Dept., Shanghai Normal Univ., Shanghai
fYear :
2009
fDate :
25-27 May 2009
Firstpage :
1895
Lastpage :
1898
Abstract :
Aiming at incommodity of extent hearing aid in the market, a new design of hearing aid is brought forward in this paper. First, the system construction is discussed, the difference between which and other hearing aids is it uses FPGA for voice processing. Second, the application of FPGA and embedded soft core Nios II is described, how to utilize SOPC builder explore Nios II embedded processor and what´s the benefit. DSP algorithm is also implemented in FPGA chip by Verilog HDL and because of strong ability of parallel processing the system based on FPGA runs faster than DSP chip does in signal processing. Third, the practicability of this device is explained through comparing with other hearing aids. The table shows the design has fine market respect because of its small size, cheap price and preferable operating performance.
Keywords :
digital signal processing chips; field programmable gate arrays; hardware description languages; hearing aids; medical signal processing; speech processing; DSP chip; FPGA chip; Nios II embedded processor; Verilog HDL; embedded soft core; parallel processing; portable hearing aid design; signal processing; system construction; voice processing; Auditory system; Computer peripherals; Data processing; Digital signal processing chips; Field programmable gate arrays; Hardware design languages; Hearing aids; PROM; Programmable logic arrays; Signal processing algorithms; DSP; FPGA; Hearing Aid; Nios II;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Industrial Electronics and Applications, 2009. ICIEA 2009. 4th IEEE Conference on
Conference_Location :
Xi´an
Print_ISBN :
978-1-4244-2799-4
Electronic_ISBN :
978-1-4244-2800-7
Type :
conf
DOI :
10.1109/ICIEA.2009.5138532
Filename :
5138532
Link To Document :
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