Debug Automation for Synchronization Bugs at RTL

Author

Dehbashi, M. ; Fey, Gorschwin

Author_Institution

Inst. of Comput. Sci., Univ. of Bremen, Bremen, Germany

fYear

2014

fDate

5-9 Jan. 2014

Firstpage

44

Lastpage

49

Abstract

One major concern in the design of Very-Large- Scale Integrated (VLSI) circuits is debugging as design size and complexity increase. Automation of the debugging process helps to decrease the development cycle of VLSI circuits and consequently to achieve a higher productivity. This paper presents an approach to automatically debug synchronization bugs due to coding mistakes at RTL. In particular, we introduce an appropriate bug model and show how synchronization bugs are differentiated from other types of bugs by our approach. The experimental results on LGsynth93 and ITC-99 benchmark suites and RTL modules of OpenRISC and OpenSPARC CPUs show diagnosis accuracy and efficiency of the approach.

Keywords

VLSI; computer debugging; integrated circuit design; reduced instruction set computing; ITC-99 benchmark suites; LGsynth93 benchmark suites; OpenRISC; OpenSPARC CPU; RTL modules; VLSI circuits; bug model; debug automation; synchronization bugs; very-large-scale integrated circuits; Circuit faults; Clocks; Computer bugs; Debugging; Integrated circuit modeling; Synchronization; Wires; SAT-based debugging; debug automation; synchronization bug;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design and 2014 13th International Conference on Embedded Systems, 2014 27th International Conference on

Conference_Location

Mumbai

ISSN

1063-9667

Type

conf

DOI

10.1109/VLSID.2014.15

Filename

6733104