• DocumentCode
    233775
  • Title

    Effective Liveness Verification Using a Transformation-Based Framework

  • Author

    Nalla, Pradeep Kumar ; Gajavelly, Raj Kumar ; Mony, Hari ; Baumgartner, Jason ; Kanzelman, Robert

  • Author_Institution
    IBM Syst. & Technol. Group, Bangalore, India
  • fYear
    2014
  • fDate
    5-9 Jan. 2014
  • Firstpage
    74
  • Lastpage
    79
  • Abstract
    Liveness properties such as "will every request eventually get a grant?" are crucial to the verification of a variety of design types. Liveness properties may only be falsified by infinite-length counterexamples, represented using lasso-shaped traces with a prefix (e.g., showing a particular request) followed by a repeating suffix loop (e.g., showing no grant). A variety of techniques have been developed to solve liveness properties, including BDD-based model checkers, various bounded liveness checking methods, and liveness-to-safety conversion. Nonetheless, the verification of such properties is computationally very challenging, no single algorithm works best, and many industrialsized liveness problems remain practically unsolvable. In this paper, we detail three approaches to solve liveness properties in our verification toolset SixthSense. The first is in the context of dynamic verification, enhancing a simulation engine to support native liveness checking. The second approach is formal, using abstraction-guided liveness-to-safety conversion for greater scalability. The third approach leverages complementary transformation algorithms to enhance the scalability of liveness checking algorithms. We additionally address automated verification of liveness properties on designs with memories, which has not received significant prior research. Experiments are provided to confirm the effectiveness of our techniques.
  • Keywords
    digital simulation; formal verification; BDD-based model checkers; SixthSense; abstraction-guided liveness-to-safety conversion; bounded liveness checking methods; infinite-length counterexamples; lasso-shaped traces; liveness properties; liveness verification; liveness-to-safety conversion; native liveness checking; repeating suffix loop; simulation engine; transformation-based framework; verification toolset; Algorithm design and analysis; Arrays; Boolean functions; Engines; Registers; Safety; Abstraction; Dynamic verification; Fairness; Formal verification; Liveness; Simulation; Transformation based verification;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design and 2014 13th International Conference on Embedded Systems, 2014 27th International Conference on
  • Conference_Location
    Mumbai
  • ISSN
    1063-9667
  • Type

    conf

  • DOI
    10.1109/VLSID.2014.20
  • Filename
    6733109