Title :
TEST SCHEDULING IN TESTABLE VLSI CIRCUITS
Author :
Kime, Charles R. ; Saluja, Kewal K.
Keywords :
Built-in self-test; Circuit testing; Hardware; Logic testing; Parallel processing; Performance evaluation; Pins; Processor scheduling; Resource management; Very large scale integration;
Conference_Titel :
Fault-Tolerant Computing, 1995, Highlights from Twenty-Five Years., Twenty-Fifth International Symposium on
Print_ISBN :
0-8186-7150-5
DOI :
10.1109/FTCSH.1995.532649
