DocumentCode :
2338102
Title :
Decoder Optimised Progressive Edge Growth Algorithm
Author :
Healy, C.T. ; de Lamare, R.C.
Author_Institution :
Dept. of Electron., Univ. of York, York, UK
fYear :
2011
fDate :
15-18 May 2011
Firstpage :
1
Lastpage :
5
Abstract :
A novel construction for irregular low density parity check (LDPC) codes based on a modification of the Progressive Edge Growth (PEG) algorithm is presented. The edge placement procedure of the PEG algorithm is enhanced by the use of the Sum-Product decoder in the design of the parity-check matrix. The proposed algorithm, like the PEG algorithm, is highly flexible in block length and rate. The codes constructed by the methods presented are tested in the AWGN channel and significant performance improvements are achieved. The flexibility of the proposed decoder optimisation operation in its application to PEG-based construction methods is then demonstrated by its use in modifying the Improved PEG (IPEG) extension to the PEG algorithm to achieve further performance gains.
Keywords :
AWGN channels; channel coding; parity check codes; product codes; AWGN channel; LDPC codes; PEG-based construction methods; decoder optimised progressive edge growth algorithm; irregular low density parity check codes; parity-check matrix; sum-product decoder; Algorithm design and analysis; Decoding; Measurement; Optimization; Parity check codes; Phase change materials; Signal to noise ratio;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Vehicular Technology Conference (VTC Spring), 2011 IEEE 73rd
Conference_Location :
Yokohama
ISSN :
1550-2252
Print_ISBN :
978-1-4244-8332-7
Type :
conf
DOI :
10.1109/VETECS.2011.5956769
Filename :
5956769
Link To Document :
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