Title :
AN IMPLICIT ENUMERATION ALGORITHM TO GENERATE TESTS FOR COMBINATIONAL LOGIC CIRCUITS
Keywords :
Circuit faults; Circuit testing; Combinational circuits; Data systems; Error correction; Linear programming; Logic circuits; Logic design; Logic testing; System testing;
Conference_Titel :
Fault-Tolerant Computing, 1995, Highlights from Twenty-Five Years., Twenty-Fifth International Symposium on
Print_ISBN :
0-8186-7150-5
DOI :
10.1109/FTCSH.1995.532656
