Minimizing Power and Skew in VLSI-SoC Clocking with Pulsed Resonance Driven De-skewing Latches

Author

Bezzam, I. ; Krishnan, Sridhar

Author_Institution

Santa Clara Univ., Santa Clara, CA, USA

fYear

2014

fDate

5-9 Jan. 2014

Firstpage

156

Lastpage

161

Abstract

An energy recovering scheme for 40% savings in clocking power with 40% driver active area reduction is demonstrated. A new resonant driver that generates tracking pulses at each transition of clock for dual edge operation across scaled frequencies is proposed. Pulsed resonant (PR) clocking is designed to drive explicit-pulsed negative setup time latches. Simulations using 45nm IBM/PTM device and interconnect models, clocking 1024 flip-flops show the reductions, compared to non-resonant clocking, operating from 2GHz/1.3V to 200MHz/0.5V. The PR frequency is set >3x the clock rate, needing only 1/10^th the inductance of previously integrated LC resonance. Skew reductions are achieved without needing to increase the interconnect widths owing to negative set-up times.

Keywords

LC circuits; UHF integrated circuits; VHF circuits; VLSI; clocks; flip-flops; integrated circuit interconnections; minimisation; system-on-chip; IBM-PTM device; PR clocking; VLSI-SoC clocking; energy recovering scheme; explicit-pulsed negative setup time latch; flip-flop; frequency 2 GHz to 200 MHz; integrated LC resonance; interconnect model; power minimization; pulsed resonance driven deskewing latch; size 45 nm; skew minimization; voltage 1.3 V to 0.5 V; Capacitance; Clocks; Delays; Flip-flops; Inductors; Latches; Resonant frequency; Clock Distribution Network; Clock Skew; Dual Edge Triggering (DET); Dynamic Voltage Frequency Scaling (DVFS); Low Power; Low Voltage; Resonant Clocking;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design and 2014 13th International Conference on Embedded Systems, 2014 27th International Conference on

Conference_Location

Mumbai

ISSN

1063-9667

Type

conf

DOI

10.1109/VLSID.2014.34

Filename

6733123