DocumentCode
2338227
Title
Performance analysis of FinFET using various gate dielectrics
Author
Nesamani, I.Flavia Princess ; Raveendran, Rijo P.C Geethanjali ; Prabha, V.Lakshmi
Author_Institution
Karunya University Coimbatore, Government College of Technology, India
fYear
2013
fDate
20-21 March 2013
Firstpage
761
Lastpage
764
Abstract
A Double Gate(DG) FinFET is designed in 30nm, 60nm technology with thickness of dielectric ranging from 1.2nm to 2.5nm and the observations are studied. Then DIBL of the device is calculated. The Double Gate(DG) FinFET is one of the promising devices to extend the CMOS technology beyond the scaling limit of conventional CMOS technology. DG FinFET has an excellent scalability and better short channel effect immunity compared to normal MOSFET device. High-k dielectric can be used in DG FinFET. While using the high-k dielectric it reduces the problems associated with gate leakage and increases the drain current. Sentaurus TCAD tool is used to find out the performance of the devices.
Keywords
CMOS integrated circuits; Dielectrics; Doping; Logic gates; Performance evaluation; Semiconductor device modeling; Silicon; DG; DIBL; HfO2 ; SiO2 ;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits, Power and Computing Technologies (ICCPCT), 2013 International Conference on
Conference_Location
Nagercoil
Print_ISBN
978-1-4673-4921-5
Type
conf
DOI
10.1109/ICCPCT.2013.6528831
Filename
6528831
Link To Document