Towards a parameterizable cycle-accurate ISS in ArchC

Author

Bechara, Charly ; Ventroux, Nicolas ; Etiemble, Daniel

Author_Institution

Embedded Comput. Lab., CEA, Gif-sur-Yvette, France

fYear

2010

fDate

16-19 May 2010

Firstpage

1

Lastpage

7

Abstract

With the increase in the design complexity of MP-SoC architectures, flexible and accurate processor simulators became a necessity for exploring the vast design space solutions. In this paper, we present a flexible cycle-accurate ISS model based on ArchC 2.0 language. The model can have a variable pipeline depth and can be integrated easily in any SoC design based on SystemC. Its performance and capabilities are demonstrated by running MiBench embedded benchmark suite, while extracting pipeline statistics for each application.

Keywords

circuit CAD; instruction sets; integrated circuit design; system-on-chip; ArchC 2.0 language; MP-SoC architectures; MiBench embedded benchmark suite; SoC design; SystemC; design complexity; design space solution; parameterizable cycle-accurate ISS; pipeline statistics; processor simulator; Computational modeling; Computer architecture; Hazards; Pipelines; Registers; Synchronization; System-on-a-chip; ADL; Design Space Exploration; ISS; System-on-Chip; cycle-accurate;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Systems and Applications (AICCSA), 2010 IEEE/ACS International Conference on

Conference_Location

Hammamet

Print_ISBN

978-1-4244-7716-6

Type

conf

DOI

10.1109/AICCSA.2010.5586945

Filename

5586945