Analysis of the floating gate defect in CMOS

The floating gate transistor is modeled using the coupling capacitances in the floating gate and the charge in the transistor gate. The location of the open in the open track influences the value of the poly-bulk and metal-poly capacitances who determines the degree of conduction of the defective transistor. The induced voltage in the floating gate and the quiescent current are estimated by means of analytical expressions. A good agreement is observed between the simple analytical expressions, simulations (SPICE) and experimental measures performed on defective circuits. It is shown that a floating gate transistor is not a stuck-open transistor and that significative values of quiescent current consumption may exist