Experiments on bridging fault analysis and layout-level DFT for CMOS designs

High quality test of complex, digital VLSI circuits require a realistic test preparation, i.e., the ability to derive test patterns to cover faults, originated by physical defects. The issues of guiding test pattern generation for a realistic gate-level fault model, and of introducing new strategies for testability enhancement, at layout level, are addressed. Experiments on standard cell digital designs show the gate-level, realistic bridging faults should be used as target faults for test preparation. Moreover, it is demonstrated that bridging faults involving fanout nodes exhibit a dominant effect on testability. Finally, it is shown that routing with testability constraints is rewarding, and that routing channels should be carefully designed for hard fault avoidance. To produce such results, a new set of tools has been developed, and is presented here