Title :
Fast multi-layer critical area computation
Author :
Xue, Hua ; Di, Chennian ; Jess, J.A.G.
Author_Institution :
Dept. of EE, Eindhoven Univ. of Technol., Netherlands
Abstract :
Based on the corner-stitching data structure, a geometrical approach to compute the critical area of a layout is presented. The run time of the proposed approach is linear to the number of patterns in a layout. Multilayer effect is taken into account so that the critical area computed for each mask layer is more accurate. The experimental results show that the method is promising for layout sensitivity analysis, yield estimation and realistic fault analysis
Keywords :
data structures; corner-stitching data structure; layout sensitivity analysis; mask layer; multi-layer critical area computation; multilayer effect; realistic fault analysis; yield estimation; Computational modeling; Data structures; Design automation; Equations; Pattern analysis; Predictive models; Sensitivity analysis; Silicon; Tiles; Yield estimation;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 1993., The IEEE International Workshop on
Conference_Location :
Venice
Print_ISBN :
0-8186-3502-9
DOI :
10.1109/DFTVS.1993.595723
