Architectural design simulation and silicon implementation of a very high fidelity decimation filter for sigma-delta data converters

Author

Kale, E.T. ; Morling, Richard C S ; Krukowski, Artur ; Devine, Don A.

Author_Institution

Westminster Univ., London, UK

fYear

1994

fDate

10-12 May 1994

Firstpage

878

Abstract

This paper reports on results from the algorithmic design and simulation of a two-path poly-phase decimation filter with 24-bit accuracy over the frequency range from dc to approximately 16 kHz. The filter is suited for very high precision data conversion applications, and has been designed for use with a fourth-order ΣΔ modulator running at 4096 kHz. This paper also reports on the fixed-point architectural design, comparative bit-level simulations and silicon implementation

Keywords

CMOS integrated circuits; analogue-digital conversion; delta modulation; digital arithmetic; digital filters; digital simulation; elemental semiconductors; signal processing; signal processing equipment; silicon; 16 kHz; 4096 kHz; Si; Si implementation; achitectural design simulation; algorithmic design; fixed-point architectural design; floating point simulation; fourth-order sigma delta modulator; frequency range; high fidelity decimation filter; precision data conversion applications; sigma-delta data converters; two-path poly-phase decimation filter; Algorithm design and analysis; Baseband; Digital filters; Digital signal processing; Filtering; Finite impulse response filter; Passband; Signal processing algorithms; Signal resolution; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Instrumentation and Measurement Technology Conference, 1994. IMTC/94. Conference Proceedings. 10th Anniversary. Advanced Technologies in I & M., 1994 IEEE

Conference_Location

Hamamatsu

Print_ISBN

0-7803-1880-3

Type

conf

DOI

10.1109/IMTC.1994.351969

Filename

351969