Embedded Complex Floating Point Hardware Accelerator

In today´s digital design, in addition to circuit delays, power consumption has become one of the main design concerns. A common solution to deal with the large execution delay and power consumption in modern processors is to use a co-processor that is capable of executing specific types of instructions in parallel with the main processor. Floating point operations are examples of such instructions that can be offloaded to a co-processor which is optimized to execute this type of complex operation with minimal delay and power. In this paper, we present a new pipelined Multiple Input Multiple Output (MIMO) ALU that is accelerated to perform complex floating point operations including addition, subtraction, multiplication and division. Our proposed Accelerated complex floating point ALU (AALU) has significantly lower delay (in clock cycles) compared to an earlier work that has an Instruction Set Extension (ISE) based architecture. Our approach can achieve up to 12x speed-up compared to the state-of-the-art designs, by completing floating point division in 91% fewer clock cycles, while significantly reducing power consumption.