Scalable Low Power FFT/IFFT Architecture with Dynamic Bit Width Configurability

In this paper, we present a novel architecture for a shared FFT/IFFT especially for OFDM transceiver applications, that can be dynamically configured to optimize the power consumption based on the operating scenario. This exploits the fact that the bit width needed to meet the required packet error rate varies across different operating scenarios while the hardware is designed for the worst case operating scenario. We propose an architecture with control signals that can be dynamically configured to reduce the average toggle activity to match that required for the specific operating scenario. We also exploit the fact that in the case of a transmit operation, the input signal comes from a known set of constellation points that may require fewer bits to represent without losing any information. These architecture modifications can be configured dynamically on a symbol-to-symbol basis based on several parameters, namely the modulation mode, input signal SNR, etc., and can be applied to most of the well known FFT architecture choices such as decimation-in-time, decimation-in-frequency with different base radix based on single-path delay feedback, multi-path delay commutator etc. The power consumption of the proposed architecture is compared with the traditional architecture in both transmit and receive modes of operation for a 64 point FFT/IFFT using pre-layout net list simulations on a 45nm library.