A Decimal/Binary Multi-operand Adder Using a Fast Binary to Decimal Converter

This paper presents a new architecture for a 7-bit Binary to BCD (BD) converter which forms the core of our proposed high speed decimal Multi-operand Adder. Our proposed design contains various improvements over existing architectures. These include an improved 7-bit BD Converter that helps in reducing the delay of the Multi-operand decimal Adder. Simulation results indicate that with a marginal increase in area, the proposed BD converter exhibits an improvement of 55% in delay and up to 27% reduction of power-delay product over earlier designs. Further the decimal Multi-operand Adder achieves up to 15% faster design and power-delay product falls to 13% when compared to previously published results.