DocumentCode
2339390
Title
Yield model for ASIC and processor chips
Author
Stapper, C.H. ; Patrick, J.A. ; Rosner, R.J.
Author_Institution
IBM Technology Products, Essex Junction, VT, USA
fYear
1993
fDate
27-29 Oct 1993
Firstpage
136
Lastpage
143
Abstract
Yield models based on chip area are inadequate for modeling the yield of CMOS ASIC and processor chips. A model based on the number of circuits was found to give more accurate results. Defect learning curves measured with DRAMs have been used successfully to project the yield of a wide variety of chips
Keywords
integrated circuit yield; ASIC; DRAMs; ROM; SRAM; chip area; defect learning curves; processor chips; yield model; Application specific integrated circuits; Area measurement; CMOS logic circuits; CMOS process; CMOS technology; Logic circuits; Manufacturing; Microprocessors; Semiconductor device measurement; Semiconductor device modeling;
fLanguage
English
Publisher
ieee
Conference_Titel
Defect and Fault Tolerance in VLSI Systems, 1993., The IEEE International Workshop on
Conference_Location
Venice
ISSN
1550-5774
Print_ISBN
0-8186-3502-9
Type
conf
DOI
10.1109/DFTVS.1993.595739
Filename
595739
Link To Document