Obstacle Avoiding Rectilinear Clock Tree Construction with Skew Minimization

Clock skew minimization plays an important role in VLSI interconnect design to assure enhanced synchronous performance of a chip. In this paper, we propose an Obstacle avoiding Rectilinear Clock tree construction algorithm navigating prioritized critical sink routing approach. Our proposed algorithm mostly focuses on delay equalization at all the sink terminals from the source, avoiding obstacle edges. The proposed method is maneuvered as follows. (1) Initially, the entire layout is divided into smaller rectangular or square sub zones, called tiles, containing subset of sink terminals. (2) Next, center of masses (CMs) of the tiles are computed based on arithmetic mean of the sink terminals associated with the tiles. Priority is assigned to the CMs based on Euclidean distance of the CMs from the source terminal. All the CMs are routed from the source to equalize delay of reaching signal to them, based on Elmore delay model. (3) Finally, a local delay balanced sub-tree is constructed in each tile, to equate delay from CM to the sink terminals, following Elmore delay structure. Elmore delay formula is adopted to calculate delay of a routing path, considering the resistive (R) and capacitive (C) effects of a wire. Proposed algorithm is run on some recent benchmark suits, and experimental results are quite encouraging.