A four-terabit single-stage packet switch with large round-trip time support

Author

Abel, F. ; Minkenberg, C. ; Luijten, R.P. ; Gusat, M. ; Iliadis, I.

Author_Institution

Zurich Res. Lab., IBM Corp., Ruschlikon, Switzerland

fYear

2002

fDate

2002

Firstpage

5

Lastpage

14

Abstract

We present the architecture and practical VLSI implementation of a 4-Tb/s single-stage switch. It is based on a combined input- and crosspoint-queued structure with virtual output queuing at the ingress, which has the scalability of input-buffered switches and the performance of output-buffered switches. Our system handles the large fabric-internal transmission latency that results from packaging up to 256 line cards into multiple racks. We provide the justification for selecting this architecture and compare it with other current solutions. With an ASIC implementation, we show that a single-stage multi-terabit buffered crossbar approach is viable today.

Keywords

CMOS integrated circuits; VLSI; application specific integrated circuits; delays; packet switching; queueing theory; telecommunication network routing; 4 Tbit/s; ASIC implementation; CMOS technology; VLSI implementation; crosspoint-queued structure; distributed packet routing switch architecture; fabric-internal transmission latency; input-buffered switch scalability; input-queued structure; line cards; output-buffered switches; round-trip time support; single-stage packet switch; virtual output queuing; Bipartite graph; CMOS technology; Centralized control; Emulation; Laboratories; Packet switching; Proposals; Scalability; Switches; Traffic control;

fLanguage

English

Publisher

ieee

Conference_Titel

High Performance Interconnects, 2002. Proceedings. 10th Symposium on

Print_ISBN

0-7695-1650-5

Type

conf

DOI

10.1109/CONECT.2002.1039251

Filename

1039251