ESD protection for mixed-signal circuits — design or test problem?

In spite of significant progress during last couple of decades, ESD still affects production yields, manufacturing costs, product quality, reliability and profitability. The objective of an ESD protection circuit is to create a harmless shunting path for the static electricity before it damages the sensitive electronic circuits. As the devices are continuously scaling down, while ESD energy remains the same, VLSIs become more vulnerable to ESD stress. This higher susceptibility to ESD damage is due to thinner gate oxides and shallower junctions. Furthermore, higher operating frequency of the scaled technologies enforces lower parasitic capacitance of the ESD protection circuits. As a result, increasing the robustness of the ESD protection circuits with minimum additional parasitic capacitance is the main challenge in state of the art CMOS processes. In this paper a general methodology to design ESD protection circuits and devices is discussed. This method is used to tackle some of the main challenges facing ESD designers in modern technologies.