• DocumentCode
    2339550
  • Title

    An FPGA configuration circuit based on JTAG

  • Author

    Zhang, Huiguo ; Tang, Yulan ; Yu, Zongguang

  • Author_Institution
    Sch. of Inf. Eng., Jiangnan Univ., Wuxi
  • fYear
    2009
  • fDate
    25-27 May 2009
  • Firstpage
    2588
  • Lastpage
    2590
  • Abstract
    An FPGA configuration circuit based on JTAG is designed. The configuration circuit has the JTAG architecture which is compatible with the IEEE standard 1149.1. Under the shift function of JTAG, a data chain for configuration is provided. The process of the configuration is controlled by three simple counters. Implemented with the CSMC 0.5 um technology, the configuration circuit has the area of 1.404 mm2, occupies the 3 percent of total FPGA area. Compared with the control scheme of complex state machine, this design is simple and has been used in an FPGA.
  • Keywords
    field programmable gate arrays; CSMC technology; FPGA configuration circuit; JTAG architecture; complex state machine; field programmable gate arrays; size 0.5 mum; the IEEE standard 1149.1; Automata; Circuit testing; Clocks; Counting circuits; Electronic equipment testing; Field programmable gate arrays; Integrated circuit interconnections; Logic arrays; Logic testing; Pins; CRC; Configuration circuit; FPGA; JTAG;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Industrial Electronics and Applications, 2009. ICIEA 2009. 4th IEEE Conference on
  • Conference_Location
    Xi´an
  • Print_ISBN
    978-1-4244-2799-4
  • Electronic_ISBN
    978-1-4244-2800-7
  • Type

    conf

  • DOI
    10.1109/ICIEA.2009.5138675
  • Filename
    5138675
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2339550