Speed-power-resolution tradeoff in switched-capacitor analog correlator circuit

We had proposed a new switched-capacitor (SC) analog correlator using balanced charge pump circuit for Code Division Multiple Access (CDMA) bus interface. The proposed circuit operates at 100 MH and dissipates 0.9 mW using 3.3 V supply voltage. We have studied the tradeoff between speed, power and input resolution of the level shifter of the analog correlator. The mismatch of the level shifter limits the input resolution of the correlator circuit. As the input resolution can be improved using large devices but with higher power dissipation. The tradeoff between resolution and power can be improved when the technology is scaled down for a given speed.