Analysis of Nanoscale Strained-Si/SiGe MOSFETs including Source/Drain Series Resistance through a Multi-iterative Technique

As one of the important technological boosters, strain in Metal-Oxide-Semiconductor Field-Effect-Transistors (MOSFETs) was first introduced in the 90 nm node and it has been continuing since then. Incorporating strain in MOSFETs allow us to increase the performance of the device without appreciable scaling of the devices. However, the presence of Source(S)/Drain(D) series resistance may degrade the performance of strained MOSFETs in the nanometer regime. Theoretical research emphasizing on the modeling and analysis of the drain current and threshold voltage of nanoscale strained MOSFETs (NSM) needs to incorporate the S/D series resistance in order to get a better insight of such devices. In this paper we have carried out a systematic analysis of drain current and threshold voltage of nanoscale strained Si/SiGe MOSFETs through a multi-iterative technique taking into account the effects of S/D series resistance. Our analysis has been further extended to study the impact of some important parameters such as strained Si layer thickness, gate oxide thickness, Ge mole fraction, and so on, on the electrical parameters of NSMs. The scaling trend of some device parameters have been modeled by analytical expressions obtained through curve-fitting technique and have been incorporated in our analysis to obtain optimized performance of NSMs.