Picosecond delay adjustment for 12.8 Gbps multiplexed testing

Author

Keezer, D.C. ; Minier, D. ; Ducharme, P.

Author_Institution

Georgia Inst. of Technol., Atlanta, GA

fYear

2008

fDate

18-20 June 2008

Firstpage

1

Lastpage

6

Abstract

A novel high-bandwidth adjustable delay circuit is described that is used for XOR-based multiplexing of multi-Gbps test signals. By precisely-aligning the phase offset of two 6.4 Gbps ATE signals, an Indium-Phosphide exclusive-OR gate is used to synthesize a double-data-rate signal with picosecond resolution and ~30 ps accuracy. The delay circuit is based on an experimentally-observed second-order effect in a SiGe variable-amplitude differential buffer. A 2-channel module for testing serial and parallel signals up to 12.8 Gbps is described. The performance of the module is demonstrated between 6.4 Gbps and 12.8 Gbps.

Keywords

Ge-Si alloys; III-V semiconductors; delay circuits; indium compounds; integrated circuit testing; logic gates; multiplexing; InP; SiGe variable-amplitude differential buffer; XOR-based multiplexing; adjustable delay circuit; bit rate 12.8 Gbit/s; bit rate 6.4 Gbit/s; delay circuit; double-data-rate signal; high-bandwidth delay circuit; indium-phosphide exclusive-OR gate; multiGbps test signals; multiplexed testing; picosecond delay adjustment; picosecond resolution; second-order effect; Circuit synthesis; Circuit testing; Delay; Germanium silicon alloys; Indium phosphide; Jitter; Signal resolution; Signal synthesis; Silicon germanium; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Mixed-Signals, Sensors, and Systems Test Workshop, 2008. IMS3TW 2008. IEEE 14th International

Conference_Location

Vancouver, BC

Print_ISBN

978-1-4244-2395-8

Electronic_ISBN

978-1-4244-2396-5

Type

conf

DOI

10.1109/IMS3TW.2008.4581626

Filename

4581626