Performance Optimization and Parameter Sensitivity Analysis of Ultra Low Power Junctionless MOSFETs

Author

Parihar, Manoj Singh ; Kranti, Abhinav

Author_Institution

Low Power Nanoelectron. Res. Group, Indian Inst. of Technol. Indore, Indore, India

fYear

2014

fDate

5-9 Jan. 2014

Firstpage

439

Lastpage

443

Abstract

The paper investigates the impact of doping concentration on the performance of Ultra Low Power (ULP) Junctionless Double Gate MOSFETs. Results show that intrinsic delay is reduced by 69% and on-off current ratio is increased by 2.5 times when junctionless transistors are designed with a doping concentration of 5×10¹⁸ cm^-3 as compared to those designed with 3×10¹⁹ cm^-3. Additional advantage of operating at 5×10¹⁸ cm^-3 is the significant reduction in the parameter sensitivity values of on-current, off-current and intrinsic delay. JL devices exhibit least sensitivity towards gate length in comparison to other parameters. The results when compared with inversion mode and under lap devices highlight the advantages of junctionless devices for ULP logic technology applications.

Keywords

MOSFET; low-power electronics; optimisation; JL device; ULP logic technology application; doping concentration; intrinsic delay; inversion mode; on-off current ratio; parameter sensitivity analysis; performance optimization; ultralow power junctionless double gate MOSFET; underlap device; Delays; Doping; Films; Logic gates; MOSFET; Sensitivity; Double Gate MOSFET; Intrinsic delay; Junctionless; Parameter Sensitivity; Ultra Low Power;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design and 2014 13th International Conference on Embedded Systems, 2014 27th International Conference on

Conference_Location

Mumbai

ISSN

1063-9667

Type

conf

DOI

10.1109/VLSID.2014.82

Filename

6733171