An insight into a digital sensor for ΔΣ modulator investigation

Even an ideal ΔΣ modulator exhibits certain nonlinear behaviour. So its comprehensive analytical description has been both an absorbing and confusing task. Hence simulation and measurement are the key factor for a successful evaluation of the ΔΣ structure. This work is about high-quality decimation filters (digital sensors) for ΔΣ modulator investigations. They are based on a two-phase (two-branch) parallel structure using recursive allpasses which are particularly suitable for decimation by a factor of two. Moreover the repeated use of a basic decimation stage (BDS) makes this structure highly modular and well fitted for silicon implementation. An important BDS with only three coefficients (1/8, 9/16 and -1/16) has been presented in detail. Applied in the five stage decimator and compatible with CMOS technology, it achieves a 20-bit processing accuracy for the passband of 20 kHz without the design complexity and cost penalties incurred in alternative approaches. The paper includes some design results with performance evaluation under fixed point arithmetic. The in-situ developed software tools are also described